1. Field of the Invention
The present invention relates to packaging technologies, and more particularly, to semiconductor packaging technologies.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. To improve electrical performance and save space, a plurality of packages can be stacked to form a package on package (PoP) structure, for example, a fan out package on package (FO PoP) structure, thereby greatly increasing the I/O count and integrating integrated circuits having different functions. Such a packaging method allows merging of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic elements having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1 for a PoP structure.
Referring to FIG. 1, the semiconductor package 1 includes a packaging substrate 10 having at least a circuit layer 101 and a semiconductor element 11 flip-chip bonded to the circuit layer 101.
The semiconductor element 11 has an active surface 11a with a plurality of electrode pads 110 and an inactive surface 11b opposite to the active surface 11a. The electrode pads 110 of the semiconductor element 11 are electrically connected to the circuit layer 101 through a plurality of, for example, solder bumps 12. Further, an underfill 13 is formed between the semiconductor element 11 and the circuit layer 101 for encapsulating the solder bumps 12.
Furthermore, an encapsulant 14 is formed on the packaging substrate 10 to encapsulate the underfill 13 and the semiconductor element 11, and a plurality of conductive through holes 17 are formed in the encapsulant 14. One ends of the conductive through holes 17 are exposed from the encapsulant 14 for mounting an electronic device such as an interposer or a packaging substrate (not shown).
However, during formation of the encapsulant 14, since the packaging substrate 10 serves as a carrier, the area of the encapsulant 14 is required to correspond to the area of the packaging substrate 10. As such, the area of the packaging substrate 10 cannot be reduced, thus resulting in a very large width of the semiconductor package 1 and hindering miniaturization of the semiconductor package 1.
Therefore, how to overcome the above-described drawbacks has become critical.